Wafer bonding is commonly employed for wafer level 3-D packaging. As technology evolves into the era of sub-micron, there is a desire to integrate/bond different wafers together to form a 2.5D or 3D integrated circuit (IC) package, also known as a wafer stack. After the wafers are bonded to form a wafer stack, the wafer stack is usually subjected to wafer back-grinding processing for reducing the wafer thickness to allow for stacking, high density packaging of ICs and revealing of interconnects for next level integration.
Edge trimming may be required before the back-grinding processes to prevent the wafer edge from chipping or breaking during the back-grinding or bumping processes. However, conventional wafer trimming processes are difficult to control and often lead to poor edge trim width control.
From the foregoing discussion, it is desirable to provide a process for trimming a wafer stack that is easy to control and simple to implement to avoid damage to the wafer edge caused by wafer back-grinding processing.